Syllabus for |
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| EDA321 - Switching circuit theory and logic design |
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| Owner: TKDAT |
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5,0 Credits (ECTS 7,5) |
| Grading: TH - Five, Four, Three, Not passed |
| Level: B |
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Department: 37 - COMPUTER SCIENCE AND ENGINEERING
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Teaching language: Swedish
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Credit distribution |
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Examination dates |
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Sp1 |
Sp2 |
Sp3 |
Sp4 |
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No Sp |
| 0105 |
Laboratory |
2,0 c |
Grading: UG |
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2,0 c
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| 0205 |
Examination |
3,0 c |
Grading: TH |
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3,0 c
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10 Mar 2006 pm V, |
19 Apr 2006 pm V, |
29 Aug 2006 am V |
In programs
TELTA ELECTRICAL ENGINEERING, Year 4 (elective)
TTFYA ENGINEERING PHYSICS, Year 4 (elective)
TDATA COMPUTER SCIENCE AND ENGINEERING, Year 2 (compulsory)
TITEA SOFTWARE ENGINEERING, Year 3 (elective)
Examiner:
Tekn lic
Arne Linde
Replaces
EDA320
Switching circuit theory and logic design
Eligibility:
For single subject courses within Chalmers programmes the same eligibility requirements apply, as to the programme(s) that the course is part of.
Course specific prerequisites
A preparatory course in Fundamentals of digital systems and computers (
e.g. EDA215, EDA311,
EDA432,
EDA451) or similar.
Aim
The course is intended to give fundamental knowledge about analysis, synthesis and optimisation of combinatorial and sequential digital networks. The course also presents the technologies used for implementing such networks. As part of the course, the student will be introduced to a modern computer-based design tool (CAD).
Goal
After completing the course, the student should be able to
- design a medium-sized digital system
- choose a suitable technology for implementing a digital system
- master the problem of hazard and synchronization in digital systems
- understand som of the underlying algorithms in a modern computer-based design tool (CAD)
Content
Combinational networks:
- Boolean algebra, axiomatic presentation and fundamental theorems.
- Boolean forms and functions. Switching functions.
- Karnaugh map representation and simplification of Boolean functions.
- Algorithms for optimization of single and multiple output combinational logic.
- Realizations of combinational logic. Static and dynamic hazards. Multilevel logic, iterative networks. Logic design with decoders, multiplexers and programmable logic devices.
Sequential networks:
- Synchronous networks. Fundamental concepts, formal definition, Mealy and Moore networks.
- State assignment methods. Algorithms for state minimization of completely and incompletely specified networks.
- Design of iterative combinational networks using sequential network techniques.
- Asynchronous networks. Fundamental concepts. Cycles and races. Race-free state assignments. Essential hazards. State minimization.
-Design for test
-Components and technologies
-VHDL for synthesis
Organisation
Lectures, exercises and labs.
Literature
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Examination
Written exam; passed laborations.