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Syllabus for

Academic year
EDA445 - MOS LSI design
 
Owner: TELTA
5,0 Credits (ECTS 7,5)
Grading: UG - Fail, pass
Level: D
Department: 37 - COMPUTER SCIENCE AND ENGINEERING


Teaching language: English

Course module   Credit distribution   Examination dates
Sp1 Sp2 Sp3 Sp4 No Sp
0103 Design exercise, part A 3,0 c Grading: UG   3,0 c    
0203 Design exercise, part B 2,0 c Grading: UG   2,0 c    

In programs

TELTA ELECTRICAL ENGINEERING, Year 4 (elective)
TDATA COMPUTER SCIENCE AND ENGINEERING, Year 3 (elective)
TDATA COMPUTER SCIENCE AND ENGINEERING - Digital Systems Design, Year 4 (elective)
TDATA COMPUTER SCIENCE AND ENGINEERING - Embedded computer systems engineering, Year 4 (elective)

Examiner:

Professor  Per Larsson-Edefors


Replaces

EFT070   MOS LSI design


Eligibility:

For single subject courses within Chalmers programmes the same eligibility requirements apply, as to the programme(s) that the course is part of.

Course specific prerequisites

To pass on the course the student must have attended EME010 Digital VLSI design and acquired a grade of 3 or higher.

Aim

In this course the student will design a complete integrated circuit in CMOS technology using commercial CAD tools.

Goal

The knowledge that the student has earned in Digital VLSI design and (possibly) Analog VLSI design shall here be applied to build a larger and, more importantly, complete chip that should possess all the qualities that enables the manufacturing of the design. The student should hereby gain knowledge on how a complete chip integration is done, in collaboration with advanced industrial design methods and an advanced CAD tool.

Content

The student will become familiar with advanced IC (ASIC) design through a chip design project, where an industrial CAD tool suite for IC design is used. The project takes a specification down to complete implementation and layout verification, and finishes with the testing of manufactured chip. Physical design issues are highlighted alongside I/O structures and design for test.

Organisation

At the introductory lecture a number of VLSI projects are presented. Students team up in groups of 2-3 and choose one project; at the same time the students get a supervisor assigned to them. We strive to have an even distribution of groups over the different project categories. From the moment a project has been chosen, the student group is responsible for keeping contact with the supervisor. Regular meetings between student group and supervisor are encouraged, but how frequently these meetings take place is up to the students.

After the introductory lecture follows a handful of lectures in the 3rd quarter in which IC design methodology, process technology, design rules, CAD tools, and I/O structures are presented.

A number of exercises are provided during the 3rd and 4th quarters; here the student rehearses basic schematic and layout design, and learns new issues regarding the assembly of many small blocks, leading to the tapeout of the entire design.

The different projects are disseminated during lectures in the 4th quarter; schematic designs are reviewed during the first lectures of Q4, whereas complete layouts are reviewed in the end of Q4.

All projects must be well documented, and a written report is required at the end of the 4th quarter. This report is very important for a successful measurement of fabricated chips.

After the 4th quarter only the best designs qualify for IC fabrication. Each supervisor makes this choice in each project category, based on quality of design and report. The critera used for selecting the best design will be presented during the course.

In June the designs are sent for fabrication. Measurement on fabricated chips and reporting of measurement results is belonging to a separate section in the beginning of the fall.

Literature

Either Jan M. Rabaey, et.al., "Digital integrated circuits: A design perspective", 2nd edition, or "CMOS VLSI Design: A Circuits and Systems Perspective" by Neil Weste/David Harris, 3rd edition.

Examination

Active participation in project. One large written report and two oral presentations.

Course elements:

  • Konstruktionsövning A (Q3, 3p) comprises schematic design of complete chip. Pass is awarded a student that can present acceptable simulation data for the complete design. The format of presentation is decided by the supervisor, but usually there is a requirement for some kind of report (and then this report is the seed for the final report which is to be handed in after Q4).
  • Konstruktionsövning B (Q4, 2p) comprises layout design of complete chip. Pass is awarded a student that hands in a final report of acceptable quality and (this is very important!) participates in the measurements of fabricated chips during early fall. The results of the testing of the chip need to be integrated with the final report from Q4.


Page manager Published: Mon 28 Nov 2016.