Syllabus for |
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| EDA455 - System on a chip - design |
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| Owner: TDATA |
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4,0 Credits (ECTS 6) |
| Grading: TH - Five, Four, Three, Not passed |
| Level: A |
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Department: 37 - COMPUTER SCIENCE AND ENGINEERING
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Teaching language: Swedish
Maximum participants: 30
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Credit distribution |
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Examination dates |
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Sp1 |
Sp2 |
Sp3 |
Sp4 |
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No Sp |
| 0103 |
Laboratory |
0,0 c |
Grading: UG |
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0,0 c
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| 0203 |
Examination |
0,0 c |
Grading: TH |
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0,0 c
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Contact examiner |
| 0303 |
Project |
4,0 c |
Grading: UG |
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4,0 c
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In programs
TELTA ELECTRICAL ENGINEERING, Year 4 (elective)
TDATA COMPUTER SCIENCE AND ENGINEERING - Digital Systems Design, Year 4 (elective)
TDATA COMPUTER SCIENCE AND ENGINEERING - Embedded computer systems engineering, Year 4 (elective)
Examiner:
Docent
Lars R Bengtsson
Eligibility:
For single subject courses within Chalmers programmes the same eligibility requirements apply, as to the programme(s) that the course is part of.
Course specific prerequisites
An important pre-requisite is that the student already has good logic design skills and has done design using a Hardware Description Language such as VHDL. This experience should include HDL simulation and synthesis to an FPGA platform. (The course EDA915 Industrial Digital Design (VHDL) , or equivalent). In addition, the student should have a good understanding of computer organization and experience with simple application development in e.g. C or C++.
Aim
The primary goal of the course is for the students to use the latest, state of the art, industrial quality design tools and methodologies to implement a complex system with an embedded processor using a single, large Field Programmable Gate Array (FPGA) chip.
This is an advanced course in digital design that addresses SOC (System On a Chip) design methods. State of the art industrial design tools will be used to create a complex system with an embedded processor using a single, large (>200K gate equivalents or higher) Field Programmable Gate Array (FPGA). The course will be organized around two laboratory projects which will present subsets of the tools and the design process, and then the students will form teams to do a complex class project. Lectures will be held in the beginning of the course to discuss the various tools and design methodologies.
The class project will require the students to implement dedicated logic tightly integrated with an embedded soft-core processor on a single FPGA. The project will have both software and hardware components that must be integrated. In addition, the students will be expected to use timing analysis and verification tools as well as pre-existing IP (specialized functional FPGA configurations).
Goal
After completing the course the students shall have:
- designed and implemented a SOC design in an FPGA device
- planned the projectwork both in time and in manpower
- done oral and written presentations
- orrally presented a research paper given to them
- participated in a seminar series where SOC research papers are presented and discussed
Content
This is an course in digital design that addresses SOC (System On a Chip) design. This is done via a proejct work and a seminar series where journal articles from the SOC area are studied.
In the project assignment, state of the art industrial design tools are used to create a complex system with an embedded processor and other IP, using a single, large Field Programmable Gate Array (FPGA).
Organisation
The course is organized around a laboratory projects which will present subsets of the tools and the design process, and then the students will form teams to do a complex class project. Lectures will be held in the beginning of the course to discuss the various tools and design methodologies.
The class project will require the students to implement dedicated logic tightly integrated with an embedded soft-core processor on a single FPGA. The project will have both software and hardware components that must be integrated. In addition, the students will be expected to use timing analysis and verification tools as well as pre-existing IP (specialized functional FPGA configurations).
Literature
Articles from journals and conferences.
Examination
Passed on the lab assignments and on the project assignment (including oral and written presentations). This is adequate for grade 3. For grade 4 or 5 (Chalmers grade), a written test must also be passed.