Syllabus for |
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| TDA955 - Hardware description and verification |
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| Owner: DCMAS |
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4,0 Credits (ECTS 6) |
| Grading: TH - Five, Four, Three, Not passed |
| Level: D |
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Department: 37 - COMPUTER SCIENCE AND ENGINEERING
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Teaching language: English
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Credit distribution |
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Examination dates |
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Sp1 |
Sp2 |
Sp3 |
Sp4 |
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No Sp |
| 0198 |
Examination |
4,0 c |
Grading: TH |
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4,0 c
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29 May 2006 am V, |
Contact examiner, |
30 Aug 2006 pm V |
In programs
TELTA ELECTRICAL ENGINEERING, Year 4 (elective)
TITEA SOFTWARE ENGINEERING, Year 4 (elective)
TITEA SOFTWARE ENGINEERING, Year 3 (elective)
TDATA COMPUTER SCIENCE AND ENGINEERING - Computer Languages, Year 4 (elective)
TDATA COMPUTER SCIENCE AND ENGINEERING - Digital Systems Design, Year 4 (elective)
TDATA COMPUTER SCIENCE AND ENGINEERING - Embedded computer systems engineering, Year 4 (elective)
TDATA COMPUTER SCIENCE AND ENGINEERING, Year 3 (elective)
DCMAS MSc PROGR IN DEPENDABLE COMPUTER SYSTEMS, Year 1
Examiner:
Professor
Mary Sheeran
Eligibility:
For single subject courses within Chalmers programmes the same eligibility requirements apply, as to the programme(s) that the course is part of.
Course specific prerequisites
Ideally you should either know about digital design or about functional programming. It is of course better to know both, but this is not necessary. If you know neither, you should probably choose a different course.
Aim
The aim of the course is to give a flavour of some industrially applied methods for description and verification of hardware, as well as some of the research in the area.
Content
What is a hardware description langauge? How is it different from an ordinary programming language? The standard hardware description language VHDL. How should circuit properties be specified? The standard formal specification language PSL and associated circuit verification methods. Formal verification via model checking. Binary decision diagrams and their use in reachability analysis and model checking. Another approach: using a functional language for hardware description. Formal verification via synchronous observers.
Organisation
The course consists of lectures, demonstrations, laborations and homework. In this course a greater emphasis will be placed on you working independently than you may be used to.
Literature
Peter J. Ashenden, The Designer's Guide to VHDL. Second Edition, Morgan Kaufmann, 2001.
OR (for Swedish speakers)
S. Sjöholm, and L. Lindh, VLSI för Konstruktion, Fourth Edition, Studentlitteratur, 2001.
Examination
Two take-home exams and a final written exam. All labs must be passed. Grading: Fail, 3, 4 or 5.