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Syllabus for

Academic year
EDA191 - VLSI computer architecture
 
Owner: TDATA
4,0 Credits (ECTS 6)
Grading: TH - Five, Four, Three, Not passed
Level: A
Department: 37 - COMPUTER SCIENCE AND ENGINEERING


Teaching language: Swedish

Course module   Credit distribution   Examination dates
Sp1 Sp2 Sp3 Sp4 No Sp
0199 Examination 4,0 c Grading: TH   4,0 c   Contact examiner,  Contact examiner,  Contact examiner

In programs

TDATA COMPUTER SCIENCE AND ENGINEERING - Digital Systems Design, Year 4 (elective)
TDATA COMPUTER SCIENCE AND ENGINEERING - Embedded computer systems engineering, Year 4 (elective)
TITEA SOFTWARE ENGINEERING, Year 4 (elective)
TITEA SOFTWARE ENGINEERING, Year 3 (elective)
TELTA ELECTRICAL ENGINEERING, Year 4 (elective)

Examiner:

Docent  Lars R Bengtsson



Eligibility:

For single subject courses within Chalmers programmes the same eligibility requirements apply, as to the programme(s) that the course is part of.

Course specific prerequisites

EDA915 Digital electronics design; EDA111 Computer architecture;
Digital circuit design knowledge

Aim

Design using Field Programmable Gate Arrays (FPGAs) is today of big
importance to companies utilizing electronics in their products. The aim of this course is to provide theoretical and practical knowledge of how a pipelined processor architecture can be realized using FPGA technology. The goals of the course are to give a deepend understanding of how a pipeline can be effectively organized, and good knowledge of how a complex digital design can be realized in an FPGA circuit.

Goal

After completing the course the students shall have:

- designed and implemented a pipelined microprocessor architecture in an FPGA device
- planned the projectwork both in time and in manpower
- evaluated different architecture solutions with respect to CPI, Tc, and execution times for some benchmark programs.
- done oral and written presentations
- orrally presented a research paper searched in research paper databases (e.g. IEEE Xplore)
- participated in a seminar series where microprocessor circuit level research papers are presented and discussed.

Content

The major part of the course is a project assignment where groups of students (typically 4) implements a microprocessor pipeline in an FPGA circuit. The result of the project is presented both orally and and in a written report. The course also includes a seminar series where research papers concerning implementation aspects (mainly circuit level) of existing microprocessor designs are studied and presented.

Organisation

The course includes a minor theoretic part, a major project assignment and a seminar series. The theoretic part is a small number of lectures dealing with:
- Methods for implementing microprocessors
- Synchronous timing; Virtex FPGA
- Design of FPGA circuits

Literature

The course uses text material from the department.

Examination

1) Participation in a seminarseries where the students (groups of typically 2) orally presents a research article concerning implementation aspects of some modern microprocessor architecture.
2) Active participation in the project. Attendance is mandatory at project meetings, the seminars, in the lab and at all presentations.
3) Successful project including written and oral presentation of it.


Page manager Published: Thu 03 Nov 2022.