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Course syllabus for

Academic year
MCC092 - Introduction to integrated circuit design
Introduktion till integrerad kretskonstruktion
Course syllabus adopted 2022-02-02 by Head of Programme (or corresponding)
Owner: MPEES
7,5 Credits
Grading: TH - Pass with distinction (5), Pass with credit (4), Pass (3), Fail
Education cycle: Second-cycle
Main field of study: Computer Science and Engineering, Electrical Engineering

Teaching language: English
Application code: 15116
Open for exchange students: Yes
Block schedule: B+
Maximum participants: 48

Module   Credit distribution   Examination dates
Sp1 Sp2 Sp3 Sp4 Summer course No Sp
0116 Examination 3,0 c Grading: TH   3,0 c   27 Oct 2022 am J,  03 Jan 2023 am J,  21 Aug 2023 am J
0216 Laboratory 3,0 c Grading: UG   3,0 c    
0316 Written and oral assignments 1,5 c Grading: UG   1,5 c    

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Lena Peterson

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General entry requirements for Master's level (second cycle)
Applicants enrolled in a programme at Chalmers where the course is included in the study programme are exempted from fulfilling the requirements above.

Specific entry requirements

English 6 (or by other approved means with the equivalent proficiency level)
Applicants enrolled in a programme at Chalmers where the course is included in the study programme are exempted from fulfilling the requirements above.

Course specific prerequisites

Basic knowledge about electric circuit theory, analog and digital electronics, logic design, and computer organization. Ability to perform engineering calculations.


The overall aim of the course is to introduce the student to the field of CMOS integrated circuit design and to give some introductory training in the use of industrial Electronic Design Automation (EDA) tools and in understanding their role in the integrated circuit design flow. Technology node independent performance models for power and speed are presented, giving the student generic tools to estimate cost and performance properties in circuits of present and future CMOS technologies.

Learning outcomes (after completion of the course the student should be able to)

  • design static CMOS logic gates (pull-up and pull-down networks) and implement these as standard cells.
  • from simple MOS transistor models, estimate static and dynamic properties of CMOS inverters and use these properties to model more complex gates.
  • derive logical-effort normalized-delay parameters from circuit diagrams or layout, and use these parameters to estimate and trade off performance measures such as critical-path delays and power dissipation in present and future CMOS technologies.
  • find critical paths in more complex combinatorial circuits, such as adders, and determine and minimise their delays.
  • analyse wire-delay-dominated cases such as clock distribution and global interconnect, and suggest suitable buffering schemes to minimize delay or delay spread.
  • design simple sequential systems that meet set-up and hold time constraints for timing circuits, including the effect of metastability in synchronisation.
  • analyze dynamic and static power consumption on circuit and chip level.and suggest suitable mitigation techniques for total energy and power.
  • use industrial-type design automation tools to design, implement and verify basic CMOS circuit elements following the design flow supported by such tools.


  • Introduction to CMOS integrated circuit design; basic building blocks, technology platforms and design tools.
  • Introduction to the circuit design flow: schematic capture, circuit simulation, layout, rule checking, and layout-vs-schematic verification. Hands-on design skill training using industrial electronic design automation (EDA) tools.
  • The MOSFET as a digital switch.
    • The two-port as a static and dynamic model.
  • The inverter as the basic digital building block
    • Static properties - the voltage transfer characteristics, switching voltage, noise margins.
    • Dynamic properties - the RC delay model, buffer sizing, process corners.
    • Dynamic switching power and static leakage power.
  • Static CMOS logic gates. Designing logic gates with pull-up and pull-down networks.
    • The two-port as a dynamic switching model. Input load capacitances and output driving capability.
    • Technology independent delay measures. Definition of logical effort, parasitic delay and electrical effort (fanout).
    • Critical path delays. Sizing gates for minimum path delay.
  • Basic layout using standard-cell layout templates.
  • The adder as a design demonstrator. Ripple carry, carry look-ahead, and prefix-tree adders.
  • Interconnect and wire delay. The RC two-port wire model. Elmore's delay model. Repeaters.
  • Latches and flip-flops. Set-up and hold time requirements. Metastability including practical mitigation techniques.
  • Static and dynamic power consumption. Power and clock distribution. Mitigation techniques for static and dynamic energy and power consumption, including clock and power gating.


The course is a sister course to the parallel course "Design of digital electronic systems" which has more of a system perspective. The course takes the student from the basic building block, the MOS Field Effect Transistor, through CMOS logic gates to sub-system blocks such as adders and data-paths in arithmetic/logic units (ALU).

The course is organized in themes with weekly lectures, home assignments, and circuit design-tasks organized as a series of hands-on laboratory exercises using industrial type electronic design automation (EDA) tools. Each laboratory session is associated with a pre-lab home assignment and a concluding post-lab discussion.


CMOS VLSI Design 4th edition, Weste & Harris, Addison Wesley, ISBN-10: 0321547748, ISBN-13: 9780321547743

Examination including compulsory elements

Compulsory laboratory exercises and compulsory weekly home assignment hand-in problems, and final written examination. To pass the course, 50 % of the points in the written examination is required. Hand-in problems can give bonus points that can be used to reach grade four or five. Bonus points cannot be used to pass the course (that is achieve grade three).

The course examiner may assess individual students in other ways than what is stated above if there are special reasons for doing so, for example if a student has a decision from Chalmers on educational support due to disability.

Page manager Published: Thu 03 Nov 2022.