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Syllabus for

Academic year
EDA322 - Digital design  
Syllabus adopted 2015-02-10 by Head of Programme (or corresponding)
Owner: TKDAT
7,5 Credits
Grading: TH - Five, Four, Three, Not passed
Education cycle: First-cycle
Major subject: Computer Science and Engineering, Electrical Engineering

Teaching language: English

Course module   Credit distribution   Examination dates
Sp1 Sp2 Sp3 Sp4 Summer course No Sp
0113 Laboratory 3,0 c Grading: UG   3,0 c    
0213 Examination 4,5 c Grading: TH   4,5 c   16 Mar 2016 pm SB   Contact examiner   25 Aug 2016 pm SB

In programs

TKELT ELECTRICAL ENGINEERING, Year 3 (compulsory elective)
TIELL ELECTRICAL ENGINEERING - Common branch of study, Year 3 (compulsory elective)
TIDAL COMPUTER ENGINEERING, Year 3 (compulsory elective)


Docent  Ioannis Sourdis


EDA320   Switching circuit theory and logic design EDA321   Theory and logic design of switching circuits

  Go to Course Homepage


In order to be eligible for a first cycle course the applicant needs to fulfil the general and specific entry requirements of the programme(s) that has the course included in the study programme.

Course specific prerequisites

A preparatory course in Fundamentals of digital systems and computers (e.g. EDA216, EDA433, EDA452) or similar.


The course is intended to give fundamental knowledge about analysis, synthesis and optimization of combinatorial and sequential digital circuits. The course also presents the technologies used for implementing such circuits. As part of the course, the student will be introduced to a modern computer-based design tool (CAD), and learn the basics of hardware description language.

Learning outcomes (after completion of the course the student should be able to)

1. Knowledge and understanding
  • describe binary arithmetic units for addition, multiplication and division.
  • describe the different storage elements used in digital circuits (latches, flip-flops, different types of memories).
  • recognize the function and uses of Reconfigurable and ASIC technologies.
  • list the differences of various types of Finite State Machines (Mealy, Moore, synchronous Mealy).
  • recognize the basics of design for testability and the basic principles behind the testing.
  • identify and describe asynchronous sequential circuits.
  • list the factors that affect the timing, power and area of a digital circuit.
2. Skills and abilities
  • minimize a Boolean function or derive its canonical form.
  • create the design specifications of a digital circuit for a given problem.
  • measure the critical path delay of a digital circuit.
  • use VHDL to describe combinatorial and sequential circuits.
  • use modern tools to perform simulation, synthesis and implementation of a digital circuit described in VHDL.
  • create test benches for VHDL designs to validate their correct functionality.
  • use FPGA technology to implement a digital hardware design.
  • define FSM encodings and perform state minimization. 
3. Judgment and approach
  • evaluate the advantages and disadvantages of different implementation technologies (ASICs, FPGAs) for digital designs, and select one for a specific design.
  • compare different design for binary arithmetic (e.g. different adder designs).
  • critically evaluate and judge a design choice in terms of power, delay, area, and be able to select the one that fits the particular design constraints.


  • Boolean Algebra and logic minimization
  • Arithmetic Units
  • Memory
  • Combinational circuits
  • Sequential circuits and Finite State Machines
  • Technologies of digital circuits (ASIC, FPGA)
  • Asynchronous circuits
  • Timing and Power consumption of digital circuits
  • Testing and design for testing
  • Hardware description languages (VHDL) for digital circuits
  • Hardware Design, test and evaluation of a simple processor


Lectures and labs.


S. Brown, Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, Third Edition


The course is examined by an individual exam given in an examination hall and 7 laboratory assignments.
The Laboratory work is carried out in groups of normally 2 students.

Page manager Published: Thu 03 Nov 2022.