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Syllabus for

Academic year
MCC091 - Introduction to integrated circuit design
 
Syllabus adopted 2015-02-11 by Head of Programme (or corresponding)
Owner: MPEES
7,5 Credits
Grading: TH - Five, Four, Three, Not passed
Education cycle: Second-cycle
Major subject: Computer Science and Engineering, Electrical Engineering
Department: 37 - COMPUTER SCIENCE AND ENGINEERING


Teaching language: English
Open for exchange students
Block schedule: B

Course module   Credit distribution   Examination dates
Sp1 Sp2 Sp3 Sp4 Summer course No Sp
0111 Examination 3,0 c Grading: TH   3,0 c   29 Oct 2015 am M,  05 Jan 2016 am M,  22 Aug 2016 am M
0211 Laboratory 3,0 c Grading: UG   3,0 c    
0311 Written and oral assignments 1,5 c Grading: UG   1,5 c    

In programs

MPCOM COMMUNICATION ENGINEERING, MSC PROGR, Year 2 (compulsory elective)
MPEPO ELECTRIC POWER ENGINEERING, MSC PROGR, Year 2 (elective)
MPEES EMBEDDED ELECTRONIC SYSTEM DESIGN, MSC PROGR, Year 1 (compulsory)

Examiner:

Bitr professor  Kjell Jeppson
Univ lektor  Lena Peterson


Replaces

EME010   Digital VLSI design MCC090   Digital integrated circuit design


  Go to Course Homepage

Eligibility:


In order to be eligible for a second cycle course the applicant needs to fulfil the general and specific entry requirements of the programme that owns the course. (If the second cycle course is owned by a first cycle programme, second cycle entry requirements apply.)
Exemption from the eligibility requirement: Applicants enrolled in a programme at Chalmers where the course is included in the study programme are exempted from fulfilling these requirements.

Course specific prerequisites

Basic knowledge about electric circuit theory, analog and digital electronics, logic design, and computer organization. Ability to perform engineering calculations.

Aim

The overall aim of the course is to introduce the student to the field of CMOS integrated circuit design and to give some introductory training in the use of industrial Electronic Design Automation (EDA) tools and in understanding their role in the integrated circuit design flow. Technology node independent performance models for power and speed are presented, giving the student generic tools to estimate cost and performance properties in circuits of present and future CMOS technologies.

Learning outcomes (after completion of the course the student should be able to)


  • conceive, design, implement, and verify the functionality of basic digital CMOS building blocks in the context of standard-cell design.

  • use simple models suitable for back-of-the-envelope calculations to predict and evaluate circuit performance measures like critical path delays and power dissipation.

  • use industrial-type design automation tools for designing basic CMOS circuit elements following the design flow supported by such tools.

  • carry out basic digital circuit design tasks within given constraints by applying suitable methods, also in a context where non-technical issues and time-to-market aspects are important.

  • describe the fundamental possibilities and limitations of digital and analog CMOS circuit technologies.

  • critically and systematically integrate knowledge to model, simulate, predict and evaluate CMOS circuit behavior, also with limited or incomplete information.

  • communicate circuit design proposals and the rationale underpinning their solutions.

Content


  • Introduction to CMOS integrated circuit design; basic building blocks, technology platforms and design tools.

  • Introduction to the circuit design flow: schematic capture, circuit simulation, layout, rule checking, and layout-vs-schematic verification. Hands-on design skill training using industrial electronic design automation (EDA) tools.

  • The MOSFET as a digital switch. The square-law model.


    • The two-port as a static and dynamic large-signal and small-signal model.

  • Basic CMOS technology.

  • The inverter as the basic digital and analog building block


    • Static properties - the voltage transfer characteristics, switching voltage, noise margins.

    • Dynamic properties - the RC delay model, buffer sizing, process corners.

    • Dynamic switching power and static leakage power.

  • Static CMOS logic gates. Designing logic gates with pull-up and pull-down networks.


    • The two-port as a dynamic switching model. Input load capacitances and output driving capability.

    • Technology independent delay measures. Definition of logical effort and parasitic delay.

    • Critical path delays. Sizing gates for minimum path delay.

  • Basic layout using standard-cell layout templates.

  • The adder as a design demonstrator. Ripple carry, carry look-ahead, and prefix-tree adders.

  • Interconnect and wire delay. The RC two-port wire model. Elmore's delay model. Repeaters.

  • Latches and flip-flops. Set-up and hold time requirements.

  • Static and dynamic power consumption. Power and clock distribution. Power gating. Clock gating.

Organisation

The course is organized as a "bottom-up" sister course to the "top-down" organized "Introduction to electronic system design". The course takes you from the basic building block, the MOS Field Effect Transistor, through CMOS logic gates to sub-system blocks like adders and data-paths in arithmetic/logic units (ALU).


The course is organized with weekly lectures, home assignments, and circuit design-tasks organized as a series of hands-on laboratory exercises using industrial type electronic design automation (EDA) tools from Cadence. Each laboratory session is associated with a pre-lab home assignment and a concluding discussion.

Literature

CMOS VLSI Design 4th edition, Weste & Harris, Addison Wesley, ISBN-10: 0321547748, ISBN-13: 9780321547743

book cover

Examination

Compulsory laboratory exercises, weekly home assignment hand-ins, and final written examination.


Page manager Published: Mon 28 Nov 2016.