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Syllabus for

Academic year
DAT110 - Methods for electronic system design and verification
Syllabus adopted 2012-02-21 by Head of Programme (or corresponding)
Owner: MPEES
7,5 Credits
Grading: TH - Five, Four, Three, Not passed
Education cycle: Second-cycle
Major subject: Computer Science and Engineering, Electrical Engineering

Teaching language: English
Open for exchange students
Block schedule: D

Course module   Credit distribution   Examination dates
Sp1 Sp2 Sp3 Sp4 Summer course No Sp
0107 Written and oral assignments 7,5 c Grading: TH   7,5 c    

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Professor  Per Larsson-Edefors

Course evaluation:

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For single subject courses within Chalmers programmes the same eligibility requirements apply, as to the programme(s) that the course is part of.

Course specific prerequisites

Strict prerequisites: DAT091/DAT092 Introduction to electronic system design.
Recommended prerequisites: Discrete mathematics and Combinatorial optimization.


In light of the fact that we can integrate billions of complicated transistors and wires on one chip, electronic system designers are forced to make use of software tools to manage design complexity and meet, for example, strict timing, power and time-to-market budgets. To apply the right software tools in the right context and in the right sequence has become a methodological challenge that rivals traditional design challenges intrinsic in logic and circuit design and verification.

The purpose of this course is to strengthen the student's proficiency in Electronic Design Automation (EDA) methods, mainly through an exposé of the algorithmic principles that are hidden in industrial Computer Aided Design (CAD) tools for electronic system design.

Learning outcomes (after completion of the course the student should be able to)

After the completion of this course, the student should be able to

  • describe the algorithmic principles of a number of important EDA techniques, such as behavioral and logic synthesis, logic simulation, static timing analysis, and power analysis
  • describe contemporary EDA design flows and their fundamental weaknesses and strengths
  • apply appropriate CAD software to electronic system design and verification problems
  • identify what design phases CAD tools are good at/not good at handling, and in what situations a designer needs to be wary of the output result produced by the CAD tool
  • critically and systematically integrate knowledge, to model, simulate, predict and evaluate features of digital ASIC backend design flows, also with limited or incomplete information
  • communicate his/her conclusions of laboratory work and in-depth term paper studies, and the knowledge and rationale underpinning these, clearly and unambiguously


The lecture series cover:

  • Electronic system design using software and hardware
  • Functional verification
  • Behavioral and logic synthesis
  • Timing analysis
  • Power analysis
  • Discrete mathematics/graph theory and optimization for Electronic Design Automation
  • Algorithms for physical design
  • Design for test and manufacturability
  • Seminars on in-depth studies (term papers)
  • Guest lectures


The pedagogical concept of the course rests on three cornerstones:

  • lectures   --   these supply the design and verification context of advanced electronic systems containing software and hardware
  • lab exercises   --   these offer comprehensive hands-on training on industrially relevant design and verification problems using state-of-the-art CAD software (Cadence RTL Compiler and SoC Encounter)
  • term paper   --   the active study into research-level texts ensures that each student can focus on an appropriate and interesting technical area and at the same time obtain training in reading research papers


Main textbook: Electronic Design Automation for Integrated Circuits Handbook - 2 Volume Set, by L. Lavagno, G. Martin, and L. Scheffer, CRC Press, 2006, ISBN 9780849330964. (This book is also available from within Chalmers, as an electronic book.)

Supplemental scientific papers for the group work on term papers.


The examination is made up of two parts:

  • Lab exercises in groups of two students on design flow, including synthesis and place-and-route for ASICs. 60% of grade is based on quality of preparation, execution and outcome in terms of lab report.
  • Group work (2-3 students) on selected topics, including a term paper, oral presentation and opposition. 40% of grade is based on quality of term paper and presentation/opposition.

Page manager Published: Mon 28 Nov 2016.