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Syllabus for

Academic year
EDA321 - Theory and logic design of switching circuits  
Syllabus adopted 2012-02-18 by Head of Programme (or corresponding)
Owner: TKDAT
7,5 Credits
Grading: TH - Five, Four, Three, Not passed
Education cycle: First-cycle
Major subject: Computer Science and Engineering, Electrical Engineering

Teaching language: English
Block schedule: LA

Course module   Credit distribution   Examination dates
Sp1 Sp2 Sp3 Sp4 Summer course No Sp
0105 Laboratory 3,0 c Grading: UG   3,0 c    
0205 Examination 4,5 c Grading: TH   4,5 c   11 Mar 2013 am M,  18 Jan 2013 am M,  29 Aug 2013 am M

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Docent  Ioannis Sourdis


EDA320   Switching circuit theory and logic design

Course evaluation:

  Go to Course Homepage


For single subject courses within Chalmers programmes the same eligibility requirements apply, as to the programme(s) that the course is part of.

Course specific prerequisites

A preparatory course in Fundamentals of digital systems and computers (e.g. EDA215, EDA432, EDA451) or similar.


The course is intended to give fundamental knowledge about analysis, synthesis and optimization of combinatorial and sequential digital networks. The course also presents the technologies used for implementing such networks. As part of the course, the student will be introduced to a modern computer-based design tool (CAD), and learn the basics of hardware description language.

Learning outcomes (after completion of the course the student should be able to)

To give a theoretical and practical base for construction of digital system. After the course

the student should be able to:

  • Transform a problem to a theoretical model.

  • Applying structured methods for analysis and synthesis of combinatorial circuits and Finite

    State Machines.

  • Describing a digital design in VHDL, perform simulation and synthesis with modern tools and

    perform tests against the target technology.

  • With the understanding, that the hardware works in parallel, be able to exploit parallelism in VHDL.

  • Function, use and limitations of programmable logic.

  • Know the basics of design for testability, and the principles behind the testing.

  • Understanding the link between VHDL and the synthesis to hardware.

Skills and abilities:

  • Simplify a function of up to five variables with Karnaugh maps.

  • Use VHDL to implement combinatorial circuits.

  • Be able to identify static and dynamic hazards, and eliminate them.

  • Be able to use the target technology¿s FPGA and CPLD in an efficient manner.

  • Have a basic understanding of how to build gates out of transistors.

  • Master the binary arithmetic such as "Carry look-ahead", multiplication, and BCD.

  • Understand and be able to use Finite State Machines of Mealy, Moore, and synchronous Mealy


  • Encode a Finite State Machines with for the target technology optimal coding and to minimize

    the number of states.

  • Be able to encode Finite State Machines of Mealy, Moore, and synchronous Mealy type in VHDL

    and understand their timing properties.

  • Be able to create test benches for VHDL designs in VHDL.

  • Know and be able to implement simpler asynchronous sequential circuits.

  • Be able to identify cycles and races in asynchronous sequential circuits and to eliminate


  • Minimize an asynchronous sequential circuit and give it a race free encoding.



Combinational networks:
- Boolean algebra, axiomatic presentation and fundamental theorems.
- Boolean forms and functions. Switching functions.
- Karnaugh map representation and simplification of Boolean functions.
- Algorithms for optimization of single and multiple output combinational logic.
- Realizations of combinational logic. Static and dynamic hazards. Multilevel logic, iterative networks. Logic design with decoders, multiplexers and programmable logic devices.

Sequential networks:
- Synchronous networks. Fundamental concepts, formal definition, Mealy and Moore networks.
- State assignment methods. Algorithms for state minimization of completely specified networks.
- Design of iterative combinational networks using sequential network techniques.
- Asynchronous networks. Fundamental concepts. Cycles and races. Race-free state assignments. Essential hazards. State minimization.

-Design for test
-Components and technologies
-HDL for synthesis


Lectures, exercises and labs.


S. Brown, Z. Vranesic, Fundamentals of Digital Logic with VHDL Design,  Third Edition


Written exam; passed laborations.

Page manager Published: Mon 28 Nov 2016.