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Syllabus for

Academic year
MCC090 - Digital integrated circuit design
 
Syllabus adopted 2009-02-20 by Head of Programme (or corresponding)
Owner: MPIES
7,5 Credits
Grading: TH - Five, Four, Three, Not passed
Education cycle: Second-cycle
Major subject: Computer Science and Engineering, Electrical Engineering
Department: 59 - MICROTECHNOLOGY AND NANOSCIENCE


Teaching language: English

Course module   Credit distribution   Examination dates
Sp1 Sp2 Sp3 Sp4 Summer course
0107 Laboratory 1,5 c Grading: UG   1,5 c    
0207 Examination 5,0 c Grading: TH   5,0 c   21 Oct 2010 am M,  13 Jan 2011 pm M,  24 Aug 2011 pm V
0307 Written and oral assignments 1,0 c Grading: UG   1,0 c    

In programs

MPCOM COMMUNICATION ENGINEERING, MSC PROGR, Year 2 (elective)
MPEPO ELECTRIC POWER ENGINEERING, MSC PROGR, Year 2 (elective)
MPIES INTEGRATED ELECTRONIC SYSTEM DESIGN, MSC PROGR, Year 1 (compulsory)

Examiner:

Bitr professor  Kjell Jeppson


Replaces

EME010   Digital VLSI design

Course evaluation:

http://document.chalmers.se/doc/646903802


Eligibility:

For single subject courses within Chalmers programmes the same eligibility requirements apply, as to the programme(s) that the course is part of.

Course specific prerequisites

Basic digital circuit design and computer organization, or equivalent.

Aim

The overall aim of the course is to introduce the student to the field of digital CMOS integrated circuit design and to the use of industrial CAD tools and their role in the application specific integrated circuit design flow.

Learning outcomes (after completion of the course the student should be able to)

* understand so much of the MOS field effect transistor that they can design basic static (and dynamic) combinational CMOS logic gates. They should also know how to optimize the gate performance in terms of speed, power dissipation, and robustness, not only as a stand-alone gate but also as a building block at the next level of hierarchy in general, and in the context of a critical timing path in particular.

* knowledge of timing circuits (latches and flip-flops) that they can understand and meet set-up and hold time constraints, and about wiring that they can solve basic problems of global clock distribution and global chip interconnect.

* insight into structured circuit design that they can design basic data path building blocks and know how to connect such blocks to a data bus, to internal registers and to control logic.

Content

MOSFET devices and CMOS technology/fabrication. MOSFET current and capacitance models. Parasitic properties of devices.
Basic static CMOS. Electrical properties: noise robustness, speed and power. Impact of parasitics and wires. Combinational CMOS logic gate design. Interconnect.
Timing circuits - latches and flip-flops. Temporal properties and synchronization. Setup and hold times.
Digital building blocks: Data-path, memory, and control.
Overview of standard-cell design flows, power conversion and distribution, and clock generation and distribution.
Survey of technology platforms from a circuits perspective.

Organisation

The course is a bottom-up organized sister course to the top-down organized "Introduction to electronic system design". The course takes you from the basic building block, the MOS Field Effect Transistor, through CMOS logic gates to sub-system blocks like data-paths, registers, and memories.

Technology node independent performance models for power and speed are presented, giving the student generic tools to estimate cost and performance properties of present and future CMOS technologies.

The course is organized with weekly lectures, home assignments and hands-on laboratory exercises on industrial type computer aided design tools.

Literature

CMOS VLSI Design 3rd edition, Weste & Harris, Addison Wesley, ISBN: 0-321-14901-7

book cover

or

Digital Integrated Circuits,
Rabaey, Chandrakasan, and Nikolic, Prentice-Hall, ISBN: 0-13-120764-4

book coverLink to book official webpage

Examination

Compulsary laboratory exercises, weekly hand-ins of home assignment solutions, and final written examination


Page manager Published: Mon 28 Nov 2016.