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Graduate courses

Departments' graduate courses for PhD-students.


Syllabus for

Academic year
SSY011 - Electrical systems
Elektriska system
Syllabus adopted 2019-02-13 by Head of Programme (or corresponding)
Owner: TIELL
7,5 Credits
Grading: TH - Five, Four, Three, Fail
Education cycle: First-cycle
Major subject: Electrical Engineering

The course is full. For waiting list, please contact the director of studies:
Teaching language: Swedish
Application code: 63127
Open for exchange students: No
Block schedule: D+
Maximum participants: 40
Only students with the course round in the programme plan

Module   Credit distribution   Examination dates
Sp1 Sp2 Sp3 Sp4 Summer course No Sp
0115 Laboratory 3,5 c Grading: UG   3,5 c    
0215 Examination 4,0 c Grading: TH   4,0 c   01 Nov 2019 am L,  08 Jan 2020 pm L,  Contact examiner

In programs

TIDAL COMPUTER ENGINEERING, Year 3 (compulsory elective)
TIELL ELECTRICAL ENGINEERING - Common branch of study, Year 3 (compulsory)


Erik Agrell

  Go to Course Homepage


SSY010   Electrical systems


In order to be eligible for a first cycle course the applicant needs to fulfil the general and specific entry requirements of the programme(s) that has the course included in the study programme.

Course specific prerequisites

Knowledge corresponding to the courses LEU470 Electrical Circuits, LEU460 Electrical Engineering and LEU430 Fundamentals of Digital Systems and Computer.


This course will provide knowledge about some methods and tools for analysis and design of analog and digital electronics.

Learning outcomes (after completion of the course the student should be able to)

  • Dimension and implement a complete system for digital transmission of audio signals including analog and digital subsystems

  • Use computer tools in the design, analysis and simulation of analog and digital electronics.

  • Handle computer software for analog electronic circuit drawing and simulation.

  • Analyse and modify existing VHDL code.

  • Use computer software for simulation of VHDL code and its synthesis in an FPGA circuit.

  • From a functional description, design a state diagram for a state machine.

  • Dimension, analyse, and implement current/voltage converters, digital/analog converters, analog/digital converters, parallel/serial converters, and serial/parallel converters.

  • Dimension, analyse, and implement signal amplifiers, power amplifiers, and active filters.

  • Design cascaded OP amplifiers in order to achieve desired frequency properties.

  • Measure and analyse the frequency properties of analog amplifiers and filters.

  • Analyse the stability of a feedback system and calculate the conditions for oscillation.

  • Describe a typical development process for electronic systems in industry.


During the course, a complete audio transmission system will be designed including audio amplifier, A/D conversion, digital serial transmission, D/A conversion, filtering, and power amplification.

Analysis and design of analog och digital electronics including the following elements: A/D and D/A conversion. Analog circuit design using Spice. Finite state machines. Description and design of digital systems using VHDL. Simulations. Calculation of upper and lower cutoff frequencies for different amplifier stages and OP amplifier circuits. Design of circuits to fulfill desired frequency properties. Feedback principles. Analysis of stability in feedback systems. Design of active analog filters.


The course includes lectures, laboratory sessions, and hand-in assignments.


Parts of "Analog elektronik" by Bengt Molin and "Elektriska mätsystem och mätmetoder" by Lars Bengtsson, which both have been used in previous courses, will be used, in combination with lecture slides, lab memo, and other material on the course web page.

Examination including compulsory elements

Written examination and presentation of results from laboratory and hand-in assignments. To pass the course, a passed written exam and passed laboratory assignments are required. The final grade is U (fail), 3, 4 or 5.

Page manager Published: Thu 04 Feb 2021.