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Syllabus for

Academic year
MCC091 - Introduction to integrated circuit design
 
Syllabus adopted 2013-02-14 by Head of Programme (or corresponding)
Owner: MPEES
7,5 Credits
Grading: TH - Five, Four, Three, Not passed
Education cycle: Second-cycle
Major subject: Computer Science and Engineering, Electrical Engineering
Department: 59 - MICROTECHNOLOGY AND NANOSCIENCE


Teaching language: English
Open for exchange students
Block schedule: B

Course module   Credit distribution   Examination dates
Sp1 Sp2 Sp3 Sp4 Summer course No Sp
0111 Examination 3,0c Grading: TH   3,0c   21 Oct 2013 am V,  14 Jan 2014 pm V,  25 Aug 2014 pm V
0211 Laboratory 3,0c Grading: UG   3,0c    
0311 Written and oral assignments 1,5c Grading: UG   1,5c    

In programs

MPCOM COMMUNICATION ENGINEERING, MSC PROGR, Year 2 (compulsory elective)
MPEPO ELECTRIC POWER ENGINEERING, MSC PROGR, Year 2 (elective)
MPEES EMBEDDED ELECTRONIC SYSTEM DESIGN, MSC PROGR, Year 1 (compulsory)

Examiner:

Bitr professor  Kjell Jeppson


Replaces

EME010   Digital VLSI design MCC090   Digital integrated circuit design

Course evaluation:

http://document.chalmers.se/doc/0230ec40-983f-4279-8fd3-5d88dbb4206f


  Go to Course Homepage

 

Eligibility:

For single subject courses within Chalmers programmes the same eligibility requirements apply, as to the programme(s) that the course is part of.

Course specific prerequisites

Basic electric circuit theory, basic analog and digital electronic circuits, and computer organization, or equivalent.

Aim

The overall aim of the course is to introduce the student to the field of CMOS integrated circuit design and to the use of industrial CAD tools and their role in the application specific integrated circuit design flow.

Learning outcomes (after completion of the course the student should be able to)

  • conceive, design, implement, and verify the functionality of basic digital and analog CMOS building blocks in the context of standard-cell design.
  • critically and systematically integrate knowledge to model, simulate, predict and evaluate CMOS circuit behavior, also with limited or incomplete information.
  • use simple models suitable for back-of-the-envelope hand calculations to predict and evaluate circuit performance measures like power dissipation and critical path delays, and to use such models for choosing the appropriate cell structure and driving capability.
  • carry out basic circuit design tasks within given constraints by applying suitable methods, also when in a context where technical aspects that are not cost effective might be sacrificed for simplicity and time-to-market aspects.
  • identify, formulate, and solve basic problems concerning subsystem structures such as adders/ALUs, and to make layout/performance trade-offs.
  • use industrial-type design automation tools for designing basic CMOS circuit elements following the design flow set up by such tools (including tools for schematic capture, circuit simulation, layout, design rule checking (DRC) and layout-vs-schematic (LVS)).
  • describe the fundamental limitations of the available circuit level design automation tools and the available CMOS technology platforms.
  • propose solutions to basic design problems and after having solved the problem, on paper or in lab, communicate their conclusions and the rationale underpinning these conclusions.

Content

  • Introduction to CMOS integrated circuit design; basic building blocks, technology platforms and circuit design tools.
  • Design flow including basic floor planning, schematic capture, circuit simulation, layout, DRC and LVS. Hands-on design skill training using Cadence electronic design automation tools.
  • The MOSFET as a digital switch and an analog small-signal amplifier
    • piecewise linear (PWL) current model with the MOSFET as a voltage-controlled resistor or current-source
    • MOSFET two-port large-signal model - the MOSFET as a resistor, or a current-source,
    • MOSFET capacitance model - adding the intrinsic input capacitance and the parasitic output capacitance to the two-port model,
    • SPICE technology files, second-order effects, technology scaling.

  • CMOS technology and fabrication. Front-end and back-end processing steps.
  • The inverter - the basic building block
    • Static properties - the voltage transfer characteristics (VTC)
      • resistive load, pseudo-NMOS load, active CMOS load

    • Dynamic properties
      • large-signal two-port inverter model: input and output parasitic capacitance, output driving capability,
      • transistor sizing for improved driving capability,
      • definition of propagation delay, rise/fall time, FO4 delay,
      • simple RC delay formula, buffer sizing, process corners

    • The inverter as an analog amplifier
      • biasing and small-signal voltage amplification, small-signal two-port model
      • analog building blocks. Single stage CMOS amplifiers. Current mirrors.

  • Static CMOS logic gates. Building logic gates with MOSFET switches. NAND, NOR, AOI, OAI, and XOR gates.
    • Sizing MOSFETs in a logic gate for equal rise and fall times.
    • Dynamic logic gate two-port model: input and output parasitic capacitance, output driving capability.
    • Definition of logical effort.
    • Critical path delays. Path efforts. Sizing gates for minimum path delay.

  • Basic layout using standard-cell layout templates.
  • Case study: 4-bit digital comparator.
  • Interconnect and wire delay.
    • Two-port RC wire model
    • Elmore's formula for wire delay estimations.
    • The use of repeaters for delay optimization.

  • Latches and flip-flops. Set-up and hold time requirements.
  • Clock generation and clock distribution. Clock gating.
  • Power dissipation. Power distribution. Power gating.
  • Carry look-ahead and prefix-tree adders.

Organisation

The course is organized as a bottom-up sister course to the top-down organized "Introduction to electronic system design". The course takes you from the basic building block, the MOS Field Effect Transistor, through CMOS logic gates to sub-system blocks like adders and data-paths.
Technology node independent performance models for power and speed are presented, giving the student generic tools to estimate cost and performance properties of present and future CMOS technologies.

The course is organized with weekly lectures, home assignments, and one or two circuit design-tasks organized as a series of hands-on laboratory exercises using industrial type electronic design automation (EDA) tools from Cadence. Each laboratory session is associated with a pre-lab home assignment and a post-lab hand-in summary and discussion.

Literature

CMOS VLSI Design 4th edition, Weste & Harris, Addison Wesley, ISBN-10: 0321547748, ISBN-13: 9780321547743

book cover

Examination

Compulsory laboratory exercises, weekly hand-ins of home assignment solutions, and final written examination.


Published: Wed 04 Apr 2018.